Overview Of I/O Memory Area; I/O Memory Area - Omron CP1L Operation Manual

Overview of I/O Memory Area

4-1 Overview of I/O Memory Area
4-1-1

I/O Memory Area

Area
CIO I/O Area Input
Area Area
Output
Area
1:1 Link Area
Serial PLC Link Area
Work Area
Work Area
Holding Area
Auxiliary Area
TR Area
Data Memory Area
Timer Completion Flags
Counter Completion Flags
Timer PVs
Counter PVs
Task Flag Area
Index Registers
Data Registers
138
This region of memory contains the data areas that can be accessed as
instruction operands. I/O memory includes the CIO Area, Work Area, Holding
Area, Auxiliary Area, DM Area, Timer Area, Counter Area, Task Flag Area,
Data Registers, Index Registers, Condition Flag Area, and Clock Pulse Area.
Size Range Task usage
1,600 bits CIO 0 to Shared by
(100 CIO 99 all tasks
words)
1,600 bits CIO 100
(100 to CIO
words) 199
1,024 bits CIO 3000
(64 words) to CIO
3063
1,440 bits CIO 3100
(90 words) to CIO
3189
14,400 CIO 3800
bits (900 to CIO
words) 6143
8,192 bits W000 to
(512 W511
words)
8,192 bits H000 to
(512 H511
words) (Note 6)
15,360 A000 to
bits (960 A959
words)
16 bits TR0 to
TR15
32,768 D00000
words to
D32767
(Note 7)
4,096 bits T0000 to
T4095
4,096 bits C0000 to
C4095
4,096 T0000 to
words T4095
4,096 C0000 to
words C4095
32 bits TK0 to
TK31
16 regis- IR0 to Function
ters IR15 separately in
each task
(Note 3)
16 regis- DR0 to
ters DR15
Note 1. A0 to A447 are read only and cannot be written. A448 to A959 are
read/write.
2. Bits can be manipulated using TST(350), TSTN(351), SET, SETB(532),
RSTB(533), and OUTB(534).
Instruction
Allocation Bit Word
access access
CP1L CPU OK OK
Units and CP-
series Expan-
sion Units or
OK OK
Expansion I/O
Units
1:1 Links OK OK
Serial PLC OK OK
Links
--- OK OK
--- OK OK
--- OK OK
--- OK ---
--- OK OK
--- No OK
(Note
2)
--- OK ---
--- OK ---
--- --- OK
--- --- OK
--- OK ---
--- OK OK
--- No OK
Section 4-1
I/O Memory
Access Change
from CX-
Read Write
Programmer
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK Note 1 Note 1
OK OK No
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK OK OK
OK No No
Indirect Specific No
address- instruc-
ing only tions only
OK OK No
Forcing
bit
status
OK
OK
OK
OK
OK
OK
OK
No
No
No
OK
OK
No
(Note 4)
No
(Note 5)
No
No
No