High-Speed Counter Terminal Allocation - Omron CP1L Operation Manual

High-speed Counters
5-1-5

High-speed Counter Terminal Allocation

Differential Phases, Up/
Down, or Pulse + Direction
184
The following diagrams show the input terminals that can be used for high-
speed counters in each CPU Unit.
Input Terminal Arrangement for CPU Units with 10 I/O Points
High-speed counter 0
(Phase B, Decrement,
or Direction input)
Upper Terminal Block
(Example: AC Power
Supply Modules)
High-speed counter 0
(Phase A, Increment,
or Count input)
High-speed counter 1
(Phase A, Increment,
or Count input)
Input Terminal Arrangement for CPU Units with 14 I/O Points
High-speed counter 0
(Phase B, Decrement, or
Direction input)
Upper Terminal Block
(Example: AC Power
Supply Modules)
High-speed counter 0
(Phase A, Increment, or
Count input)
High-speed counter 1
(Phase A, Increment, or
Count input)
Input Terminal Arrangement for CPU Units with 20 I/O Points
High-speed counter 0
(Phase B, Decrement, or
Direction input)
Upper Terminal Block
(Example: AC Power
Supply Modules)
High-speed counter 0
(Phase A, Increment, or
Count input)
High-speed counter 1
(Phase A, Increment, or
Count input)
L1 L2/N COM 01
00 02
L1 L2/N CO M 0 1
0 0
L1 L2/N COM 01 0 3
00 0 2
Section 5-1
High-speed counter 1
(Phase B, Decrement,
or Direction input)
High-speed counter 1
(Phase Z or Reset input)
03 05
04
High-speed counter 0
(Phase Z or Reset input)
High-speed counter 1
(Phase B, Decrement, or
Direction input)
High-speed counter 1
(Phase Z or Reset input)
03 05 07 NC
02 04 0 6 NC NC
High-speed counter 0
(Phase Z or Reset input)
High-speed counter 1
(Phase B, Decrement, or
Direction input)
High-speed counter 1
(Phase Z or Reset input)
05 07 09 11
04 06 0 8 10
High-speed counter 0
(Phase Z or Reset input)
N C