E Memory Map - Omron CP1L Operation Manual

PLC Memory Addresses
PLC memory addresses are set in Index Registers (IR00 to IR15) to indirectly address I/O memory. Normally,
use the MOVE TO REGISTER (MOVR(560)) and MOVE TIMER/COUNTER PV TO REGISTER
(MOVRW(561)) instructions to set PLC memory addresses into the Index Registers.
Some instructions, such as DATA SEARCH (SRCH(181)), FIND MAXIMUM (MAX(182)), and FIND MINIMUM
(MIN(183)), output the results of processing to an Index Register to indicate an PLC memory address.
There are also instructions for which Index Registers can be directly designated to use the PLC memory
addresses stored in them by other instructions. These instructions include DOUBLE MOVE (MOVL(498)),
some symbol comparison instructions (=L, <>L, <L, >L, <=L, and >=L), DOUBLE COMPARE (CMPL(060)),
DOUBLE DATA EXCHANGE (XCGL(562)), DOUBLE INCREMENT BINARY (++L(591)), DOUBLE DECRE-
MENT BINARY (––L(593)), DOUBLE SIGNED BINARY ADD WITHOUT CARRY (+L(401)), DOUBLE SIGNED
BINARY SUBTRACT WITHOUT CARRY (–L(411)), SET RECORD LOCATION (SETR(635)), and GET
RECORD LOCATION (GETR(636)).
The PLC memory addresses all are continuous and the user must be aware of the order and boundaries of the
memory areas. As reference, the PLC memory addresses are provided in a table at the end of this appendix.
Note Directly setting PLC memory addresses in the program should be avoided whenever possible. If PLC
memory addresses are set in the program, the program will be less compatible with new CPU Unit mod-
els or CPU Units for which changes have been made to the layout of the memory.
Memory Configuration
There are two classifications of the RAM memory (with battery backup) in a CP-series CPU Unit.
Parameter Areas: These areas contain CPU Unit system setting data, such as the PLC Setup, CPU Bus Unit
Setups, etc. An illegal access error will occur if an attempt is made to access any of the parameter areas from
an instruction in the user program.
I/O Memory Areas: These are the areas that can be specified as operands in the instructions in user pro-
grams.
Appendix E
Memory Map
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