Omron CP1L Operation Manual page 687

Auxiliary Area Allocations by Address
Addresses Name
Word Bits
A528 A528.00 Serial Port 2
to Error Flags
A528.07 (CP1L M-
type CPU
Units)
Serial Port 1
Error Flags
(CP1L L-
type CPU
Units)
A528.08 Serial Port 1
to Error Code
A528.15 (CP1L M-
type CPU
Units)
A529 All FAL/FALS
Number for
System
Error Simu-
lation
A531 A531.00 High-speed
Counter 0
Reset Bit
A531.01 High-speed
Counter 1
Reset Bit
Function
These flags indicate what kind of
error has occurred at the serial port 2
of a CP1L M-type CPU Unit; they are
automatically turned OFF when the
serial port 2 is restarted.
(These flags are not valid in periph-
eral bus mode and only bit 5 is valid
in NT Link mode.)
PLC Link Polling Unit:
Bit 05: ON for timeout error.
PLC Link Polled Unit:
Bit 03: ON for framing error.
Bit 04: ON for overrun error.
Bit 05: ON for timeout error.
These bits can be cleared by the CX-
Programmer.
These flags indicate what kind of
error has occurred at the serial port 1
of a CP1L L-type CPU Unit; they are
automatically turned OFF when the
serial port 1 is restarted.
(These flags are not valid in periph-
eral bus mode and only bit 5 is valid
in NT Link mode.)
PLC Link Polling Unit:
Bit 05: ON for timeout error.
PLC Link Polled Unit:
Bit 03: ON for framing error.
Bit 04: ON for overrun error.
Bit 05: ON for timeout error.
These bits can be cleared by the CX-
Programmer.
These flags indicate what kind of
error has occurred at the serial port 1
of a CP1L M-type CPU Unit; they are
automatically turned OFF when the
serial port 1 is restarted.
(These flags are not valid in periph-
eral bus mode and only bit 5 is valid
in NT Link mode.)
PLC Link Polling Unit:
Bit 13: ON for timeout error.
PLC Link Polled Unit:
Bit 11: ON for framing error.
Bit 12: ON for overrun error.
Bit 13: ON for timeout error.
These bits can be cleared by the CX-
Programmer.
Set a dummy FAL/FALS number to
use to simulate the system error
using FAL(006) or FALS(007).
When FAL(006) or FALS(007) is exe-
cuted and the number in A529 is the
same as the one specified in the
operand of the instruction, the sys-
tem error given in the operand of the
instruction will be generated instead
of a user-defined error.
When the reset method is set to
Phase-Z signal + Software reset, the
corresponding high-speed counter's
PV will be reset if the phase-Z signal
is received while this bit is ON.
When the reset method is set to Soft-
ware reset, the corresponding high-
speed counter's PV will be reset in
the cycle when this bit turns ON.
Settings Status
after
mode
change
Bits 00 and 01: Retained Cleared
Not used.
Bit 02: ON for
parity error.
Bit 03: ON for
framing error.
Bit 04: ON for
overrun error.
Bit 05: ON for
timeout error.
Bits 06 and 07:
Not used.
Bits 08 and 09: Retained Cleared
Not used.
Bit 10: ON for
parity error.
Bit 11: ON for
framing error.
Bit 12: ON for
overrun error.
Bit 13: ON for
timeout error.
Bits 14 and 15:
Not used.
0001 to 01FF Retained Cleared
hex: FAL/FALS
numbers 1 to
511
0000 or 0200
to FFFF hex:
No FAL/FALS
number for sys-
tem error simu-
lation. (No error
will be gener-
ated.)
--- Retained Cleared
--- Retained Cleared
Appendix D
Status at Write Related
startup timing Flags,
Settings
--- ---
--- ---
--- ---
--- ---
--- ---
653