5-3-10 Memory Allocations - Omron CP1L Operation Manual

Inverter Positioning

5-3-10 Memory Allocations

Built-in Input Area
Input terminal block
Word Bit
CIO 0 00
(See note 1.)
01
02
03
04
05
06(See note 2.) Normal input 6
07(See note 2.) Normal input 7
08 (See note 2.) Normal input 8
09 (See note 2.) Normal input 9
10 (See note 2.) Normal input 10 Pulse output 0: Origin proximity input signal
11 (See note 2.) Normal input 11 Pulse output 1: Origin proximity input signal
Built-in Output Area
Default
Normal inputs
Normal input 0
Normal input 1
Normal input 2
Normal input 3
Normal input 4
Normal input 5
Note (1) The above table shows only allocations related to inverter positioning.
(2) Bits 08 to 11 are not supported by CPU Units with 14 I/O Points. Bits 06
to 11 are not supported by CPU Units with 10 I/O Points.
(3) If inverter positioning 1 is used with a CPU Unit with 14 I/O Points, origin
searches (i.e., the origin proximity input signal) cannot be used.
This area is not used for inverter positioning.
When inverter positioning is enabled, bits 00 to 03 in CIO 100 can be used as
normal outputs 0 to 3. The corresponding pulse output and PWM output can-
not be used.
Pulse output origin searches enabled
Origin search
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Pulse output 0: Origin proximity input signal
(CPU Units with 14 I/O (See note 3.))
Pulse output 1: Origin proximity input signal
(CPU Units with 14 I/O (See note 3.))
Pulse output 0: Origin proximity input signal
(CPU Units with 10 I/O (See note 3.))
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Pulse output 0: Origin input signal (CPU
Units with 10 I/O (See note 3.))
Pulse output 0: Origin input signal
Pulse output 1: Origin input signal
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(CPU Units with 20, 30,40 or 60 I/O)
(CPU Units with 20, 30,40 or 60 I/O)
Section 5-3
Inverter positioning
enabled
High-speed counter 0:
Phase A
High-speed counter 0:
Phase B
High-speed counter 1:
Phase A
High-speed counter 1:
Phase B
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