Intel ® E7501 Chipset; Intel E7501 Memory Controller Hub (Mch) - Intel Pentium M Processor Design Manual

®
1.3.3 Intel
®
The Intel
•
The Intel
the MCH).
•
The Intel
•
The Intel
The chipset components communicate through Hub Interfaces (HIs). The MCH provides four Hub
Interface connections: one HI1.5 for the ICH3-S and three HI2.0s for high-speed I/O using Intel
P64H2 components. The Hub Interfaces are point-to-point and therefore only support two
components (the MCH plus one I/O device). Therefore, the system supports a maximum of three
Intel P64H2 devices.
®
1.3.3.1 Intel E7501 Memory Controller Hub (MCH)
The MCH is a 1005-ball FC-BGA package. For this platform, the MCH supports the following
functionality:
•
Platform System Bus:
— Supports single Intel
system bus (2X address, 4X data)
— Supports PSB peak bandwidth of 3.2 Gbytes/s (400 MHz)
— Supports Intel Pentium M processor 32-bit system bus addressing model
— 12 deep in-order queue, two deep defer queue
•
Platform Memory Bus:
— Single or dual channel DDR memory support
— 144-bit wide, DDR200 memory interface with memory peak bandwidth of 3.2 Gbytes/s
— Supports x72, ECC, registered DDR200 using 128-Mb, 256-Mb and 512-Mb DRAMs
— Supports a maximum of 4 Gbytes of memory
— Error correction:
Dual Channel supports Single 4-bit Error Correct, Double 4-bit Error Detect (S4EC/
D4ED) using Intel
Single Channel supports Single bit Error Correct, Double bit Error Detect (SEC/DED)
using Intel
— Supports up to 32 simultaneous open pages
•
I/O:
— Provides Hub Interface 1.5 (HI1.5) connection for ICH3-S (Hub Interface_A):
- 266 Mbytes/s point-to-point connection for ICH3-S with parity protection
- 8-bit wide, 66 MHz base clock, 4X data transfer
- Parallel termination mode for longer trace lengths
- 64-bit inbound addressing, 32-bit outbound addressing
— Provides three Hub Interface 2.0 (HI2.0) Connections for Intel P64H2 devices (Hub
Interfaces B, C and D):
Design Guide
®
Intel Pentium
E7501 Chipset
E7501 Chipset consists of three major components:
®
E7501 Chipset Memory Controller Hub (referred to throughout this document as
®
82801CA I/O Controller Hub 3 (hereafter referred to as ICH3-S).
®
82870P2 PCI/ PCI-X 64-bit Hub 2 (abbreviated to Intel
®
Pentium
®
x4 Single Device Data Correction (x4 SDDC)
®
x4 Single Device Data Correction (x4 SDDC)
®
M Processor and Intel
®
M Processor at 100 MHz (x4 transfers) - use 400 MHz
®
E7501 Chipset Platform
Introduction
®
P64H2).
27