Register 3: Domain Access Control Register; Register 5: Fault Status Register - Intel PXA255 User Manual

Configuration
7.2.4

Register 3: Domain Access Control Register

Table 7-9. Domain Access Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
D15 D14
reset value: unpredictable
Bits
31:0
7.2.5

Register 5: Fault Status Register

The Fault Status Register (FSR) indicates which fault has occurred, which could be either a
prefetch abort or a data abort. Bit 10 extends the encoding of the status field for prefetch aborts and
data aborts. The definition of the extended status field is found in
Architecture" on page
event is found in the debug control and status register (CP14, register 10). When bit 9 is set, the
domain and extended status field are undefined.
Upon entry into the prefetch abort or data abort handler, hardware will update this register with the
source of the exception. Software is not required to clear these fields.
Table 7-10. Fault Status Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:11
10
9
8
7:4
3:0
7-8
D13 D12 D11 D10
Access
Read / Write
2-11. Bit 9 indicates that a debug event occurred and the exact source of the
Access
Read-unpredictable / Write-as-Zero
Read / Write
Read / Write
Read-as-zero / Write-as-Zero
Read / Write
Read / Write
D9 D8 D7 D6 D5
Access permissions for all 16 domains - The meaning
of each field can be found in the ARM Architecture
Reference Manual.
Reserved
Status Field Extension (X)
This bit is used to extend the encoding of the Status field,
when there is a prefetch abort [See
page 2-12] and when there is a data abort [See
Table 2-14 on page
Debug Event (D)
This flag indicates a debug event has occurred and that
the cause of the debug event is found in the MOE field of
the debug control register (CP14, register 10)
= 0
Domain - Specifies which of the 16 domains was being
accessed when a data abort occurred
Status - Used along with the X-bit above to determine the
type of cycle type that generated the exception. See
"Event Architecture" on page 2-11
Intel® XScale™ Microarchitecture User's Manual
8 7 6 5 4 3
D4 D3 D2 D1
Description
Section 2.3.4, "Event
8 7 6 5 4 3
X D 0 Domain Status
Description
Table 2-13 on
2-13].
2 1 0
D0
2 1 0