Integrated Memory Controller Channel Control Registers; Mc_Channel_0_Dimm_Reset_Cmd; Mc_Channel_1_Dimm_Reset_Cmd; Mc_Channel_2_Dimm_Reset_Cmd - Intel I7-900 DESKTOP PROCESSOR - DATASHEET VOLUME 2 Datasheet

Register Description
Device:
Function: 1
Offset:
Access as a Dword
9:8
5:4
1:0
2.10 Integrated Memory Controller Channel Control
Registers
2.10.1

MC_CHANNEL_0_DIMM_RESET_CMD

MC_CHANNEL_1_DIMM_RESET_CMD

MC_CHANNEL_2_DIMM_RESET_CMD

Integrated Memory Controller DIMM reset command register. This register is used to
sequence the reset signals to the DIMMs.
Device:
Function: 0
Offset:
Access as a Dword
Bit
2
1
0
Datasheet
3
C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh
Logical Channel2.
Index 010 of the Interleave List. Bits determined from the matching
TAD_DRAM_RULE mode.
00 = Logical channel 0
RW -
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved
Logical Channel1.
Index 001 of the Interleave List. Bits determined from the matching
TAD_DRAM_RULE mode.
00 = Logical channel 0
RW -
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved
Logical Channel0.
Index 000 of the Interleave List. Bits determined from the matching
TAD_DRAM_RULE mode.
00 = Logical channel 0
RW -
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved
4, 5, 6
50h
Reset
Type
Value
BLOCK_CKE.
RW 0
When set, CKE will be forced to be deasserted.
ASSERT_RESET.
RW 0
When set, Reset will be driven to the DIMMs.
RESET.
Reset the DIMMs. Setting this bit will cause the Integrated Memory Controller
WO 0
DIMM Reset state machine to sequence through the reset sequence using the
parameters in MC_DIMM_INIT_PARAMS.
Description
59