Memory Map - NXP Semiconductors MPC5644A Reference Manual

Development Trigger Semaphore (DTS)
The XBAR Master ID should not be confused with the Master Port number
of the XBAR. See
for details.
Tools must access the DTS registers (DTS_ENABLE, DTS_STARTUP, and DTS_SEMAPHORE)
through the Nexus Read/Write Access mechanism of the e200z4 core. JTAG accesses through either core
appear as if the access is via the core and therefore will not have the same level of access as a Nexus R/W
access.
38.4

Memory map

Table 38-2 shows the memory map of the Development Trigger Semaphore module registers. Three 32-bit
registers are implemented. The rest of the memory map (0xC3F9_C00C through 0xC3F9_FFFF) is
reserved.
Address
DTS_BASE (0xC3F9_C000) DTS_ENABLE
DTS_BASE + 0x0004
DTS_BASE + 0x0008
DTS_BASE + 0x000C –
DTS_BASE + 0xFFFF
1
Only certain types of accesses are allowed. See separate description.
38.5 Register descriptions
38.5.1 DTS Output Enable Register (DTS_ENABLE)
This DTS_ENABLE register controls the DTS Trigger Output (DTO) and whether DTO is active on the
EVTO output pin of the device.
Access to the DTS_SEMAPHORE and DTS_STARTUP registers are
unaffected by the state of this register.
1696
NOTE
Chapter 9, Multi-Layer AHB Crossbar Switch
Table 38-2. DTS Module
Register
DTS output enable register
DTS_STARTUP DTS startup register
DTS_SEMAPHORE DTS semaphore register
Figure 38-4 shows the format of the DTS_ENABLE register.
NOTE
MPC5644A Microcontroller Reference Manual, Rev. 6
Description Size (bits)
32
32
32
Reserved
(XBAR),
Access
1
Restricted R/W
1
Restricted R/W
1
Restricted R/W
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