Ieee 1149.1-2001 (Jtag) Tap - NXP Semiconductors MPC5644A Reference Manual

TCODE (6 bits)
msb
37.5.3

IEEE 1149.1-2001 (JTAG) TAP

The NPC block uses the IEEE 1149.1-2001 TAP for accessing registers. Each of the individual Nexus
blocks on the device implements a TAP controller for accessing its registers as well. TAP signals include
TCK, TDI, TMS, and TDO. There may also be other blocks on the MCU that use the TAP and implement
a TAP controller. The value of the JCOMP input controls ownership of the port between Nexus and
non-Nexus blocks sharing the TAP.
Refer to the IEEE 1149.1-2001 specification for further detail on electrical and pin protocol compliance
requirements.
The NPC implements a Nexus controller state machine that transitions based on the state of the IEEE
1149.1-2001 state machine shown in
IEEE-ISTO 5001-2010 standard. It is shown in
The instructions implemented by the NPC TAP controller are listed in
NEXUS-ENABLE instruction is 0b0000. Each unimplemented instruction acts like the BYPASS
instruction. The size of the NPC instruction register is 4-bits.
Instruction name
NEXUS-ENABLE
BYPASS
Data is shifted between TDI and TDO starting with the least significant bit as illustrated in
This applies for the instruction register and all Nexus tool-mapped registers.
MSB
TDI
Freescale Semiconductor
1 2
FIELD #1
lsb msb
Figure 37-7. Transmission sequence of messages
Figure 37-9. The Nexus controller state machine is defined by the
Figure
Table 37-10. Implemented instructions
Private/Public Opcode
public 0x0 Activate Nexus controller state machine to read and write NPC
registers.
private 0xF NPC BYPASS instruction. Also the value loaded into the NPC
IR upon exit of reset.
Selected Register
Figure 37-8. Shifting data into register
MPC5644A Microcontroller Reference Manual, Rev. 6
3
FIELD #2
lsb msb
37-10.
Table 37-10. The value of the
Description
Nexus Port Controller (NPC)
lsb
Figure 37-8.
LSB
TDO
1685