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Address: DTS_BASE+0x0008
0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
1
The e200z4 core and eDMA modules can set bits in the DTS_SEMAPHORE register but cannot clear them—writes
by the core and eDMA are bitwise ORed to the contents of the register. Nexus can only read this register but all bits
are cleared after the read operation.
Name
ST[31:0]
Semaphore Trigger
When a core or eDMA writes a logical '1' to a bit, the bit is set. A write of '0' by the core or DMA does
not change the state of the bit.
• All register bits are set to '1' by a device reset.
• A JTAG reset does not change the state of this register.
• The register can be accessed, with restrictions, by any core, DMA or any Nexus RWA.
• For the core or DMA, only 32-bit write or read accesses are valid.
• A core or DMA valid read access returns the current value of the register and leaves the register
unchanged.
0: No flag
1: Flag is set
38.6
Example application
The calibration process of a new engine requires real-time access to calibration tables and the ability to
update the tables in real-time
signal to an external device pin to notify an external tool that data is available. The tool can then retrieve
the data.
In this type of application the DTS_SEMAPHORE register and DTS Trigger Output (DTO) signal provide
a mechanism to notify the calibration tool that the calibration variable or variables (or sets of
measurements), up to 32, have been updated with new values and are available for the tool to access.
1. MPC5644A devices also include an MMU modification feature, which enables real-time switching of calibration tables.
Freescale Semiconductor
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Figure 38-6. DTS_SEMAPHORE register
Table 38-5. DTS_SEMAPHORE field descriptions
1
. The DTS module enables this capability by enabling software to assert a
MPC5644A Microcontroller Reference Manual, Rev. 6
Development Trigger Semaphore (DTS)
Access: Restricted R/W
7
8
9
10
11
0
0
0
0
0
23
24
25
26
27
0
0
0
0
0
Description
1
12
13
14
15
0
0
0
0
28
29
30
31
0
0
0
0
1699
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