Jtagc Block Instructions - NXP Semiconductors MPC5644A Reference Manual

JTAG Controller (JTAGC)
36.5.3.1 Enabling the TAP controller
The JTAGC TAP controller is enabled by setting JCOMP to the JTAGC enable value. The JTAGC TAP
controller is enabled by setting JCOMP to a logic 1 value.
36.5.3.2 Selecting an IEEE 1149.1-2001 register
Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC
block instructions while the JTAGC is enabled. Instructions are shifted in via the Select-IR-Scan path and
loaded in the Update-IR state. At this point, all data register access is performed via the Select-DR-Scan
path.
The Select-DR-Scan path is used to read or write the register data by shifting in the data (LSB first) during
the Shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the Capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the Update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting may be terminated once the required number of bits have been
acquired.
36.5.4

JTAGC block instructions

The JTAGC block implements the IEEE 1149.1-2001 defined instructions listed in
section gives an overview of each instruction; refer to the IEEE 1149.1-2001 standard for more details. All
undefined opcodes are reserved.
Instruction
IDCODE
SAMPLE/PRELOAD
SAMPLE
EXTEST
HIGHZ
CLAMP
ACCESS_AUX_TAP_x
ACCESS_AUX_TAP_NPC
ACCESS_AUX_TAP_ONCE
ACCESS_AUX_TAP_eTPU
1666
Table 36-7. JTAG Instructions
Code[4:0]
00001 Selects device identification register for shift
00010 Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
00011 Selects boundary scan register for shifting and sampling without
disturbing functional operation
00100 Selects boundary scan register while applying preloaded values
to output pins and asserting functional reset
01001 Selects bypass register while three-stating all output pins and
asserting functional reset
01100 Selects bypass register while applying preloaded values to output
pins and asserting functional reset
10000–11110 Grants one of the auxiliary TAP controllers ownership of the TAP
as shown in the cells below. The number of auxiliary TAP
controllers sharing the port is 4.
10000 Enables access to the NPC TAP controller
10001 Enables access to the primary OnCE TAP controller (Primary
CPU)
10010 Enables access to the eTPU Nexus TAP controller
MPC5644A Microcontroller Reference Manual, Rev. 6
Table
Instruction summary
Freescale Semiconductor
36-7. This