External Signal Description - NXP Semiconductors MPC5644A Reference Manual

Microcontroller
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Nexus Port Controller (NPC)
37.3

External signal description

37.3.1
Overview
The NPC pin interface provides for the transmission of messages from Nexus blocks to the external
development tools and for access to Nexus client registers. The NPC pin definition is outlined in
Table
37-3.
Name
EVTO_B
JCOMP
MDO
MSEO
TCK
TDI
TDO
TMS
1
The pull is not implemented in this block. Pullup/pulldown devices are implemented in the pads.
2
Following a power-on reset, MDO[0] remains asserted until power-on reset is exited and the system clock
achieves lock.
3
TDO output buffer enable is negated when the NPC is not in the Shift-IR or Shift-DR states. A weak pull may
be implemented on TDO at the SoC level.
37.3.2
Detailed signal descriptions
This section describes each of the signals listed in
(TCK) input from the pin is not a direct input to the NPC. The NPC requires two separate input clocks for
TCK clocked logic, one for posedge (rising edge TCK) logic and one for negedge (falling edge TCK)
logic. Both clocks are derived from the pin TCK, and generated external to the NPC.
37.3.2.1
EVTO_B — Event Out
Event Out (EVTO) is an output pin that is asserted upon breakpoint occurrence to provide breakpoint
status indication. The EVTO output of the NPC is generated based on the values of the individual EVTO
signals from all Nexus blocks that implement the signal.
37.3.2.2
JCOMP - JTAG Compliancy
The JCOMP signal provides the ability to share the TAP. The NPC TAP controller is enabled when JCOMP
is set to the NPC enable encoding, otherwise the NPC TAP controller remains in reset.
1676
Table 37-3. NPC signal properties
Port
Auxiliary
Event Out pin
JTAG
JTAG Compliancy and TAP Sharing Control
Auxiliary
Message Data Out pins
Auxiliary
Message Start/End Out pins
JTAG
Test Clock Input
JTAG
Test Data Input
JTAG
Test Data Output
JTAG
Test Mode Select Input
Table 37-3
MPC5644A Microcontroller Reference Manual, Rev. 6
Function
in more detail.Note that the JTAG test clock
1
Reset State
Pull
0b1
Down
2
0
0b11
Down
Up
3
High Z
Up
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