Modes Of Operation - NXP Semiconductors MPC5644A Reference Manual

• Generates asynchronous reset signal for Nexus blocks based on JCOMP input and power-on reset
status
• System clock locked status indication via MDO[0] following power-on reset
37.2.3

Modes of operation

The NPC block uses the JCOMP input and an internal power-on reset indication as its primary reset
signals. Upon exit of reset, the mode of operation is determined by the Port Configuration Register (PCR)
settings.
37.2.3.1 Reset
The NPC block is asynchronously placed in reset when either power-on reset is asserted, JCOMP is not
set for Nexus access or the TAP controller state machine is in the Test-Logic-Reset state. Holding TMS
high for five consecutive rising edges of TCK guarantees entry into the Test-Logic-Reset state regardless
of the current TAP controller state. Following negation of power-on reset, the NPC remains in reset until
the system clock achieves lock. The NPC is unaffected by other sources of reset. While in reset, the
following actions occur:
• The TAP controller is forced into the Test-Logic-Reset state
• The auxiliary output port pins are negated
• The TDI, TMS, and TCK TAP inputs are ignored (when in power-on reset or JCOMP not set for
NPC operation only)
• Registers default back to their reset values
37.2.3.2 Disabled-Port Mode
In disabled-port mode, auxiliary output pin port enable signals are negated, thereby disabling message
transmission. Any debug feature that generates messages can not be used. The primary features available
are Class 1 features and read/write access to the registers. Class 1 features include the ability to trigger a
breakpoint event indication through EVTO.
37.2.3.3 Full-Port Mode
Full-port mode (FPM) is entered by asserting the MCKO_EN and FPM bits in the PCR. All trace features
are enabled or can be enabled by writing the configuration registers via the TAP. The number of MDO pins
available is device-specific.
37.2.3.4 Reduced-Port Mode
Reduced-port mode (RPM) is entered by asserting the MCKO_EN bit and negating the FPM bit in the
PCR. All trace features are enabled or can be enabled by writing the configuration registers via the TAP.
The number of MDO pins available is device-specific.
Freescale Semiconductor
MPC5644A Microcontroller Reference Manual, Rev. 6
Nexus Port Controller (NPC)
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