Initialization/Application Information - NXP Semiconductors MPC5644A Reference Manual

36.6

Initialization/application information

The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC block and enable access to registers, the following sequence is required:
1. Set the JCOMP signal to the JTAGC enable value, thereby enabling the JTAGC TAP controller.
2. Load the appropriate instruction for the test or action to be performed.
Freescale Semiconductor
MPC5644A Microcontroller Reference Manual, Rev. 6
JTAG Controller (JTAGC)
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