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DTS_SEMAPHORE register
written via a Nexus Read/Write Access.
Nexus Read/Write Accesses use the load/store bus of the core to perform
accesses, but Nexus accesses have a different Master ID than normal core
load/stores.
e200z4
eDMA
FlexRay
EBI
38.3.1
DTS register access
A summary of accesses to all DTS registers by bus masters is provided in
32-bit accesses are valid. The effect of write accesses, that are not 32 bits, is not defined.
Register
DTS_ENABLE
DTS_STARTUP
DTS_SEMAPHORE
1
Nexus Read/Write access via an external tool.
2
A read of the DTS_SEMAPHORE register by either Nexus Read/Write Access module is destructive and clears all
bits in the register.
Access to DTS module registers is controlled based on the XBAR Master ID of the accessing module. The
table below shows the XBAR Master IDs for each of port.
1. DTS_SEMAPHORE bits are cleared automatically when read through the Nexus/JTAG port.
Freescale Semiconductor
1
. Similarly, the DTS_ENABLE and DTS_STARTUP registers can only be
XBAR Slave Port
XBAR Master ID
Figure 38-3. DTS device connections
Table 38-1. DTS register access effects
32-bit Read
1
RWA
e200z4
eDMA
Data
Data
Data
Data
Data
Data
Data and
Data
Data
2
Clear
MPC5644A Microcontroller Reference Manual, Rev. 6
NOTE
Peripheral Bus
DTS Trigger Output
XBAR Master ID
Table
1
FlexRay
RWA
Data
Data
No effect
Data
Data
No effect
Data
No effect
Development Trigger Semaphore (DTS)
NPC
(DTO)
EVTO Pin
38-1. Note that only proper
32-bit Write
e200z4
eDMA
FlexRay
No effect
No effect
No effect
No effect
Bit OR
Bit OR
No effect
1695
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