System Bus Clock And Processor Clocking; System Bus Reset And Configuration Timings For Cold Reset - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Electrical Specifications
2.7

System Bus Clock and Processor Clocking

The BCLKn and BCLKp inputs control the operating frequency of the processor system
bus interface. All processor system bus timing parameters are specified with respect to
the falling edge of BCLKn and rising edge of BCLKp. The address pins A[21:17]# will be
used to specify the system bus frequency during reset. The processor will ensure that
the correct bus/core ratio is elected based on the bus frequency that is specified during
reset.
Cold Reset Sequence:
• The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
• RESET# must be asserted before PWRGOOD is asserted.
• The duration from the assertion of PWRGOOD to the deassertion of RESET# must
be 1 millisecond minimum.
• After RESET# is deasserted, all the configuration, including pins A[21:17]#, must
remain valid for 2 BCLKs (minimum) to 3 BCLKs (maximum).
• BCLK is shown as a time reference to the BCLK period. It is not a requirement that
this is BCLKn or BCLKp signal.
• Configuration signals other than A[21:17]# must be asserted 4 BCLKs prior to the
deasserted edge of RESET# and must remain valid for 2 BCLKs (minimum) to 3
BCLKs (maximum) after the deasserted edge of RESET#.
Figure 2-5
PWRGOOD for cold reset.
Figure 2-5.

System Bus Reset and Configuration Timings for Cold Reset

BCLK
PWRGOOD
RESET#
Bus Ratio
(A[21:17]#)
Additional
Configuration
Signals
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
outlines the timing relationship between the configuration pins, RESET# and
T
C
T = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
A
T = 1 ms minimum for cold reset
B
T = Bus ratio signals must be asserted no later than RESET#
C
T = 2 BCLKs minimum, 3 BCLKs maximum
D
T = 4 BCLKs minimum
E
T = 2 BCLKs minimum, 3 BCLKs maximum
F
t t t t
-4 -3 -2 -1
T
B
T
E
t t t t
0 1 2 3
T
A
T
D
T
F
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