Opcode Tracking During Loop Mode; Instruction Pipeline Timing Diagram - Motorola MC68340 User Manual

Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regardless
of the presence of valid data in IRA, the contents of IRB are invalidated when IPIPE is
asserted. If IRA contains valid data, the data is copied into IRB (IRA
stage is revalidated.
Assertion of IPIPE for two clock cycles indicates the start of a new instruction and
subsequent replacement of data in IRC. This action causes a full advance of the pipeline
(IRB IRC and IRA
Data loaded into IRA propagates automatically through subsequent empty pipeline stages.
Signals that show the progress of instructions through IRB and IRC are necessary to
accurately monitor pipeline operation. These signals are provided by IRA and IRB validity
bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set, and
the validity bit of the stage supplying the data is negated.
Because instruction execution is not timed to bus activity, IPIPE is synchronized with the
system clock, not the bus. Figure 5-29 illustrates the timing in relation to the system clock.
IR
CLKOUT
IPIPE
EXTENSION
WORD USED
Figure 5-29. Instruction Pipeline Timing Diagram
IPIPE should be sampled on the falling edge of the clock. The assertion of IPIPE for a
single cycle after one or more cycles of negation indicates use of the data in IRB (advance
of IRA into IRB). Assertion for two clock cycles indicates that a new instruction has started
(IRB IRC and IRA
an instruction is beginning execution—the opcode is loaded into IRC by the transfer.
In some cases, instructions using immediate addressing begin executing and initiate a
second pipeline advance simultaneously at the same time. IPIPE will not be negated
between the two indications, which implies the need for a state machine to track the state
of IPIPE . The state machine can be resynchronized during periods of inactivity on the
signal.
5.6.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to
work normally during loop mode. IFETCH indicates all instruction fetches up through the
point that data begins recirculating within the instruction pipeline. IPIPE continues to
signal the start of instructions and the use of extension words even though data is being
recirculated internally. IFETCH returns to normal operation with the first fetch after exiting
loop mode.
5-88
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IRB). IRA is refilled during the next instruction fetch bus cycle.
IR IR
IR IRB IRC
INSTRUCTION
START
IRB transfers have occurred). Loading IRC always indicates that
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IR IR
EXTENSION
WORD USED
IRB), and the IRB
IR IR
. . .
IRB IRC
INSTRUCTION
START
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