Motorola MC68340 User Manual page 366

Integrated processor with dma
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POT2–POT0—Prescaler Output Tap
If PCLK is set, these bits encode which of the prescaler's output taps act as the counter
clock. A division of the selected clock is applied to the counter as listed in Table 8-4.
MODE2–MODE0—Operation Mode
These bits select one of the eight modes of operation for the timer as listed in Table 8-5.
Refer to 8.3 Operating Modes for more information on the individual modes.
MODE2
0
0
0
0
1
1
1
1
OC1–OC0—Output Control
These bits select the conditions under which TOUTx changes (see Table 8-6). These
bits may have a different effect when in the input capture/output compare mode.
Caution should be used when modifying the OC bits near timer events.
8-22
Freescale Semiconductor, Inc.
Table 8-4. POT Encoding
POT2
POT1
POT0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
Table 8-5. MODEx Encoding
MODE1
MODE0
0
0
Input Capture/Output Compare
0
1
Square-Wave Generator
1
0
Variable Duty-Cycle Square-Wave Generator
1
1
Variable-Width Single-Shot Pulse Generator
0
0
Pulse-Width Measurement
0
1
Period Measurement
1
0
Event Count
1
1
Timer Bypass (Simple Test Mode)
Table 8-6. OCx Encoding
OC1
OC0
0
0
Disabled
0
1
Toggle Mode
1
0
Zero Mode
1
1
One Mode
MC68340 USER'S MANUAL
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Division of
Selected Clock
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
Divide by 256
OPERATION MODE
TOUTx MODE
MOTOROLA

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