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CCR1, CCR2
15
14
13
12
INTB
INTN
INTE
ECO
RESET:
U
U
U
U
U = Unaffected by reset
INTB—Interrupt Breakpoint
Setting the interrupt breakpoint bit sets the BRKP bit in the CSR. The logic AND of INTB
and BRKP generates an interrupt request.
1 = Enables an IRQ when a breakpoint is recognized and the channel is the bus
master.
0 = Does not enable an IRQ when a breakpoint is recognized and the channel is
the bus master.
INTN—Interrupt Normal
1 = Enables an IRQ when the channel finishes a transfer without an error condition
(CSR DONE bit is set).
0 = Does not enable an IRQ when the channel finishes a transfer without an error
condition.
INTE—Interrupt Error
1 = Enables an IRQ when the channel encounters an error on source read (CSR
BES bit is set), destination write (CSR BED bit is set), or configuration for
channel setup (CSR CONF bit is set).
0 = Does not enable an IRQ when the channel encounters an error on source read,
destination write, or configuration for channel setup.
ECO—External Control Option
If request generation is programmed to be internal (REQ bits = 00), this bit has no
effect.
Single-Address Mode—This bit defines the direction of transfer.
1 = If request generation is programmed to be external (REQ = 1x), the requesting
device receives the data (read from memory), and the control signals ( DREQ ,
DACK , and DONE ) are used by the requesting device to write data during the
source (read) portion of the transfer.
0 = If request generation is programmed to be external (REQ = 1x), the requesting
device provides the data (write to memory), and the control signals ( DREQ ,
DACK , and DONE ) are used by the requesting device to provide data during
the destination (write) portion of the transfer.
MOTOROLA
Freescale Semiconductor, Inc.
11
10
9
8
SAPI
DAPI
SSIZE
U
U
U
U
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
DSIZE
REQ
U
U
U
U
$788, $7A8
3
2
1
0
BB
S/D
STR
U
U
U
0
Supervisor/User
6- 27
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