Bus Arbitration - Motorola MC68340 User Manual

occurs during the stacking operation, the second error is considered a double bus fault.
When a double bus fault occurs, the MC68340 halts and asserts HALT. Only a reset
operation can restart a halted MC68340. However, bus arbitration can still occur (see 3.6
Bus Arbitration). A second bus error or address error that occurs after exception
processing has completed (during the execution of the exception handler routine or later)
does not cause a double bus fault. A bus cycle that is retried does not constitute a bus
error or contribute to a double bus fault. The MC68340 continues to retry the same bus
cycle as long as the external hardware requests it.
Reset can also be generated internally by the halt monitor (see Section 5 CPU32).

3.6 BUS ARBITRATION

The bus design of the MC68340 provides for a single bus master at any one time, either
the MC68340 or an external device. One or more of the external devices on the bus can
have the capability of becoming bus master for the external bus, but not the MC68340
internal bus. Bus arbitration is the protocol by which an external device becomes bus
master; the bus controller in the MC68340 manages the bus arbitration signals so that the
MC68340 has the lowest priority. External devices that need to obtain the bus must assert
the bus arbitration signals in the sequences described in the following paragraphs.
Systems having several devices that can become bus master require external circuitry to
assign priorities to the devices so that, when two or more external devices attempt to
become bus master at the same time, the one having the highest priority becomes bus
master first. The sequence of the protocol is as follows:
1. An external device asserts BR .
2. The MC68340 asserts BG to indicate that the bus is available.
3. The external device asserts BGACK to indicate that it has assumed bus mastership.
The MC68340 does not place CS3–CS0 in a high-impedance
state after reset or when the bus is granted to an external
master.
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to BR . To guarantee operand coherency, BG is only asserted at the end of an
operand transfer. Additionally, BG is not asserted until the end of a read-modify-write
operation (when RMC is negated) in response to a BR signal. When the requesting device
receives BG and more than one external device can be bus master, the requesting device
should begin whatever arbitration is required. When the external device assumes bus
mastership, it asserts BGACK and maintains BGACK during the entire bus cycle (or
cycles) for which it is bus master. The following conditions must be met for an external
device to assume mastership of the bus through the normal bus arbitration procedure: 1) it
must have received BG through the arbitration process, and 2) BGACK must be inactive,
indicating that no other bus master has claimed ownership of the bus.
3-40
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