Iack Cycle Timing Diagram - Motorola MC68340 User Manual

S0
CLKOUT
SIZ1–SIZ0
FC3–FC0
A31–A0,
AS
DS
IACKx
18
R/W
DSACK0
DSACK1
D15-D0
*
Up to two wait states may be inserted by the processor between states S0 and S1.
MOTOROLA
Freescale Semiconductor, Inc.
*
0–2 CLOCKS
6
11
9
21
Figure 11-9. IACK Cycle Timing Diagram
MC68340 USER'S MANUAL
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S1 S2 S3 S4
14
12
9A
46
31A
47A
31
27
S5
8
13
20
28
29
29A
11-17