Motorola MC68340 User Manual page 153

Integrated processor with dma
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Opcode
ABCD
Source 10 + Destination 10 + X
ADD
Source + Destination
ADDA
Source + Destination
ADDI
Immediate Data + Destination
ADDQ
Immediate Data + Destination
ADDX
Source + Destination + X
AND
Source
ANDI
Immediate Data
ANDI to CCR
Source
ANDI to SR
If supervisor state
the Source
else TRAP
ASL,ASR
Destination Shifted by count
Bcc
If (condition true) then PC + d
BCHG
~( number of Destination)
~( number of Destination)
Destination
BCLR
~( number of Destination)
0
bit number of Destination
BGND
If (background mode enabled) then
enter background mode
else Format/Vector offset
PC
SR
(Vector)
BKPT
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BRA
PC + d
BSET
~( number of Destination)
1
bit number of Destination
BSR
SP – 4
BTST
– ( number of Destination)
CHK
If Dn < 0 or Dn > Source then TRAP
CHK2
If Rn < lower bound or
If Rn > upper bound
then TRAP
CLR
0
Destination
CMP
Destination — Source
CMPA
Destination — Source
CMPI
Destination — Immediate Data
CMPM
Destination — Source
5-16
Freescale Semiconductor, Inc.
Table 5-2. Instruction Set Summary
Operation
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
CCR
CCR
SR
SR
Destination
PC
Z;
bit number of
Z;
–(SSP)
–(SSP)
–(SSP)
PC
PC
Z;
SP; PC
(SP); PC + d
Z;
cc
cc
MC68340 USER'S MANUAL
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ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD ea ,Dn
ADD Dn, ea
ADDA ea ,An
ADDI # data ea
ADDQ # data ea
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND ea Dn
AND Dn, ea
ANDI # data ea
ANDI # data ,CCR
ANDI # data ,SR
ASd Dx,Dy
ASd # data ,Dy
ASd ea
Bcc label
BCHG Dn, ea
BCHG # data ea
BCLR Dn, ea
BCLR # data ea
BGND
BKPT # data
BRA label
BSET Dn, ea
BSET # data ea
PC
BSR label
BTST Dn, ea
BTST # data ea
CHK ea ,Dn
CHK2 ea ,Rn
CLR ea
CMP ea ,Dn
CMPA ea ,An
CMPI # data ea
CMPM (Ay)+,(Ax)+
Syntax
MOTOROLA

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