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The circuit shown in Figure 10-3 is the typical circuit recommended by Statek Corporation,
for 32768 kHz crystal, part number CX-IV. It is recommended to start with these values,
but parameter values may need to be adjusted to compensate for variables in layout.
Figure 10-3. Statek Corporation Crystal Circuit
A separate power pin (V
of the device powered down and to provide increased noise immunity for the clock circuits.
The source for V
CCSYN
(see Figure 10-4) should be placed as close as possible to the V
stable operating frequency.
Additionally, the PLL requires that an external low-leakage filter capacitor, typically in the
range of 0.01 to 0.1 F, be connected between the XFC and V
capacitor should provide 50-M
clock mode without PLL, the XFC pin can be left open. Smaller values of the external filter
capacitor provide a faster response time for the PLL, and larger values provide greater
frequency stability. Figure 10-4 depicts examples of both an external filter capacitor and
bypass capacitors for V
10-2
Freescale Semiconductor, Inc.
330 k
XTAL
MC68340
20 M
EXTAL
Figure 10-2. Sample Crystal Circuit
470 k
XTAL
MC68340
22 M
EXTAL
) is used to allow the clock circuits to operate with the rest
CCSYN
should be a quiet power supply, and external bypass capacitors
insulation but should not be electrolytic. For external
.
CCSYN
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
4.7 pF
32.768 kHz
10 pF
10 pF
32.768 kHz
20 pF
CCSYN
CCSYN
pin to ensure a
pins. The XFC
MOTOROLA
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