Word Operand To 16-Bit Port, Aligned; Long-Word Operand To 8-Bit Port, Aligned - Motorola MC68340 User Manual

3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the
address bus with the desired address and the size pins to indicate a word operand.
WORD OPERAND
DATA BUS
CYCLE 1
For a read operation, the slave responds by placing the data on bits 15–0 of the data bus
and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the
MC68340 reads the data on the data bus and terminates the cycle.
For a write operation, the MC68340 drives the word operand on bits 15–0 of the data bus.
The slave device then reads the entire operand from bits 15–0 of the data bus and asserts
DSACK1 to terminate the bus cycle.
3.2.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the
address bus with the desired address and the SIZx pins to indicate a long-word operand.
LONG-WORD OPERAND
DATA BUS
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
For a read operation, shown in Figure 3-3, the slave responds by placing the most
significant byte of the operand on bits 15–8 of the data bus and asserting DSACK0 to
indicate an 8-bit port. The MC68340 reads the most significant byte of the operand (byte
0) from bits 15–8 and ignores bits 7–0. The MC68340 then decrements the transfer size
counter, increments the address, initiates a new cycle, and reads byte 1 of the operand
from bits 15–8 of the data bus. The MC68340 repeats the process of decrementing the
transfer size counter, incrementing the address, initiating a new cycle, and reading a byte
to transfer the remaining two bytes.
For a write operation, shown in Figure 3-4, the MC68340 drives the two most significant
bytes of the operand on bits 15–0 of the data bus. The slave device then reads only the
most significant byte of the operand (byte 0) from bits 15–8 of the data bus and asserts
DSACK0 to indicate reception and an 8-bit port. The MC68340 then decrements the
transfer size counter, increments the address, and writes byte 1 of the operand to bits
15–8 of the data bus. The MC68340 continues to decrement the transfer size counter,
increment the address, and write a byte to transfer the remaining two bytes to the slave
device.
3-10
Freescale Semiconductor, Inc.
OP0 OP1
15 0
D15 D8 D7 D0
OP0 OP1
OP0
OP1
31 23 15
D15 D8 D7 D0
OP0 (OP1)
(OP1)
OP1
OP2 (OP3)
OP3 (OP3)
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SIZ1 SIZ0 A0
1 0 0
OP2 OP3
0
7
SIZ1 SIZ0 A0
0 0 0
1 1 1
1 0 0
0 1 1
DSACK1 DSACK0
0 X
DSACK1 DSACK0
1 0
1 0
1 0
1 0
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