Bkpt Timing For Single Bus Cycle; Bkpt Timing For Forcing Bdm; Bkpt /Dsclk Logic Diagram - Motorola MC68340 User Manual

SHIFT_CLK
FORCE_BGND
BKPT_TAG
BKPT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FREEZE
Figure 5-24. BKPT Timing for Single Bus Cycle
Figure 5-25 depicts the timing of the BKPT /FREEZE method. In both cases, the serial
clock is left high after the final shift of each transfer. This technique eliminates the
possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session.
As mentioned previously, all timing within the CPU is derived from the rising edge of the
clock; the falling edge is effectively ignored.
SHIFT_CLK
FORCE_BGND
BKPT_TAG
BKPT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FREEZE
Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As
the name implies, FORCE_BGND is used to force a transition into BDM by the assertion
of BKPT . FORCE_BGND can be a short pulse or can remain asserted until FREEZE is
asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is
applied.
FORCE_BGND
BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the
assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first
DSCLK.
5-72
Freescale Semiconductor, Inc.
Figure 5-25. BKPT Timing for Forcing BDM
BKPT_TAG
SHIFT_CLK
. . . . .
S1
S2
RESET
R
Figure 5-26. BKPT /DSCLK Logic Diagram
MC68340 USER'S MANUAL
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BKPT/DSCLK
Q
Q
MOTOROLA