Table of Contents
Advertisement
***************************************************************************
* DMA Channel 1 equates
DMACH1
EQU $780
DMAMCR1 EQU $0
* Channel 1 register offsets from channel 1 base address
DMAINT1
EQU $4
DMACCR1
EQU $8
DMACSR1
EQU $A
DMAFCR1
EQU $B
DMASAR1
EQU $C
DMADAR1
EQU $10
DMABTC1
EQU $14
SARADD
EQU $6001
DARADD
EQU $10000
NUMBYTE
EQU $14
***************************************************************************
***************************************************************************
* Initialize DMA Channel 1
***************************************************************************
LEA
MODBASE+DMACH1,A0 Pointer to channel 1
* Initialize DMA channel 1 MCR
* Normal Operation, ignore FREEZE, dual-address mode. ISM field at 0. Make
* CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup.
* Supervisor/user reg. unrestricted, MAID field at 4. IARB priority at 8.
MOVE.W
#$00C8,(A0)
* Clear channel control reg.
* Clear STR (start) bit to prevent the channel from starting a transfer early.
CLR.W
DMACCR1(A0)
* Initialize interrupt reg.
* Interrupt priority at 7, interrupt vector at $42.
MOVE.W
#$0742,DMAINT1(A0)
* Initialize channel status reg.
* Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup.
MOVE.B
#$7C,DMACSR1(A0)
* Initialize function code reg.
* DMA space, supervisor data space for source and destination.
MOVE.B
#$DD,DMAFCR1(A0)
* Initialize source operand address
6-44
Freescale Semiconductor, Inc.
Offset from MBAR for channel 1 regs
MCR for channel 1
interrupt register channel 1
control register channel 1
status register channel 1
function code register channel 1
source address register channel 1
destination address register channel 1
byte transfer count register channel 1
source address is an ODD address
destination address is and EVEN address
number of bytes to transfer
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Advertisement
Table of Contents
