Motorola MC68340 User Manual page 278

Integrated processor with dma
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Dual-Address Mode—This bit defines which device generates requests.
1 = If request generation is programmed to be external (REQ = 1x), the source
device generates the request, and the control signals ( DREQ , DACK , and
DONE ) are part of the source (read) portion of the transfer.
0 = If request generation is programmed to be external (REQ = 1x), the destination
device generates the request, and the control signals ( DREQ , DACK , and
DONE ) are part of the destination (write) portion of the transfer.
SAPI—Source Address Pointer Increment
1 = The SAR is incremented by 1, 2, or 4 after each transfer, according to the source
size. The address that is written into the SAR points to a memory block and is
incremented to complete the data transfer.
0 = The SAR is not incremented during operand transfer. The address that is written
into the SAR points to a peripheral device and is used for the complete data
transfer.
DAPI—Destination Address Pointer Increment
1 = The DAR is incremented by 1, 2, or 4 after each transfer, according to the source
size. The address that is written into the DAR points to a memory block and is
incremented to complete the data transfer.
0 = The DAR is not incremented during operand transfer. The address that is written
into the DAR points to a peripheral device and is used for the complete data
transfer.
SSIZE—Source Size Control Field
This field controls the size of the source (read) bus cycle that the DMA channel is
running. Table 6-2 defines these bits.
6-28
Freescale Semiconductor, Inc.
Table 6-2. SSIZEx Encoding
Bit 9
Bit 8
0
0
0
1
1
0
1
1
*External logic is required to complete a long-
word transfer.
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Definition
Long Word*
Byte
Word
Not Used
MOTOROLA

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