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EXAMPLE B: A system uses error detection and correction on RAM contents. The
designer may:
1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to
indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is
valid, assert DSACK (case 1).
2. Delay DSACK until data is verified and assert BERR with or without DSACK if
data is in error (case 3). This initiates exception processing for software handling of
the condition.
3. Return DSACK prior to data verification; if data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
4. Return DSACK prior to data verification; if data is invalid, assert BERR and HALT
on the next clock cycle (case 6). The memory controller can then correct the RAM
prior to or during the automatic retry.
Table 3-4. DSACK , BERR , and HALT Assertion Results
Case
Control
Num
Signal
1
DSACK
BERR
HALT
DSACK
2
BERR
HALT
DSACK
3
BERR
HALT
4
DSACK
BERR
HALT
5
DSACK
BERR
HALT
DSACK
6
BERR
HALT
NOTES:
N — Number of the current even bus state (e.g., S2, S4, etc.)
A — Signal is asserted in this bus state
NA — Signal is not asserted in this state
X — Don't care
S — Signal was asserted in previous state and remains asserted in this state
MOTOROLA
Freescale Semiconductor, Inc.
Asserted on Rising
Edge of State
N
N + 2
A
S
NA
NA
NA
X
A
S
NA
NA
A/S
S
NA/A
X
A
S
NA
X
A
X
NA
A
NA
NA
NA/A
X
A
S
A/S
S
A
X
NA
A
NA
A
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Result
Normal cycle terminate and continue.
Normal cycle terminate and halt; continue
when HALT negated.
Terminate and take bus error exception,
possibly deferred.
Terminate and take bus error exception,
possibly deferred.
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
3- 33
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