Intel SR1625UR - Server System - 0 MB RAM Service Manual page 131
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Upper Nibble
MSB
8h
LED
#7
0xEDh
O
0xEEh
O
Memory Reference Code Progress Codes (Not accompanied by a beep code)
0xB0h
O
OxB1h
O
0xB2h
O
0xB3h
O
0xB4h
O
OxB6h
O
0xB8h
O
0xB9h
O
0xBAh
O
0xBBh
O
0xBFh
O
Host Processor
0x04h
X
0x10h
X
0x11h
X
0x12h
X
0x13h
X
®
Intel
Server System SR1625UR Service Guide
Table 9. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
O=On; X=Off
4h
2h
1h
8h
#6
#5
#4
#3
O
O
X
O
O
O
X
O
X
O
O
X
X
O
O
X
X
O
O
X
X
O
O
X
X
O
O
X
X
O
O
X
X
O
O
O
X
O
O
O
X
O
O
O
X
O
O
O
X
O
O
O
X
X
X
X
X
X
O
X
X
X
O
X
X
X
O
X
X
X
O
X
Lower Nibble
LSB
4h
2h
1h
#2
#1
#0
O
X
O
Population Error: RDIMMs and UDIMMs
cannot be mixed in the system
O
O
X
Mismatch Error: more than 2 Quad
Ranked DIMMS in a channel.
X
X
X
Chipset Initialization Phase
X
X
O
Reset Phase
X
O
X
DIMM Detection Phase
X
O
O
Clock Initialization Phase
O
X
X
SPD Data Collection Phase
O
O
X
Rank Formation Phase
X
X
X
Channel Training Phase
X
X
O
Memory Test Phase
X
O
X
Memory Map Creation Phase
X
O
O
RAS Initialization Phase
O
O
O
MRC Complete
O
X
X
Early processor initialization where
system BSP is selected
X
X
X
Power-on initialization of the host
processor (bootstrap processor)
X
X
O
Host processor cache initialization
(including AP)
X
O
X
Starting application processor
initialization
X
O
O
SMM initialization
Description
113
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