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22.3 ROM Correction Control Register
ROM correction is controlled by the correction control register (CORCN).
(1) Correction control register (CORCN)
This register controls whether or not the correction branch request signal is generated when the fetch address
matches the correction address set in correction address registers 0 and 1. The correction control register
consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1). The
correction enable flags enable or disable the comparator match detection signal, and correction status flags show
the values are matched.
CORCN is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 22-3. Format of Correction Control Register (CORCN)
Address: FF8AH After reset: 00H
Symbol
7
CORCN
0
COREN1
0
1
CORST1
0
1
COREN0
0
1
CORST0
0
1
Note Bits 0 and 2 are read-only bits. Bits 0 and 2 are set (1) only when a match is detected by the comparator.
Do not set these bits to 1 by software.
CHAPTER 22 ROM CORRECTION
Note
R/W
6
5
0
0
Correction address register 1 and fetch address match detection control
Disabled
Enabled
Correction address register 1 and fetch address match detection flag
Not detected
Detected
Correction address register 0 and fetch address match detection control
Disabled
Enabled
Correction address register 0 and fetch address match detection flag
Not detected
Detected
User's Manual U15798EJ2V0UD
4
3
2
0
COREN1
CORST1
1
0
COREN0
CORST0
421
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