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5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operation mode including
the standby mode.
• Main system clock
• Subsystem clock
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XT
• CPU clock
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CPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined by using the processor clock control register
(PCC).
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (3.2 µ s @10 MHz
operation) is selected (PCC = 04H). Main system clock oscillation stops while a low level is applied to the RESET
pin.
(b) With the main system clock selected, one of the five minimum instruction execution times (0.2 µ s, 0.4 µ s,
0.8 µ s, 1.6 µ s, 3.2 µ s, @10 MHz operation) can be selected by setting PCC.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. To reduce
power consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the
subsystem clock.
(d) The PCC can be used to select the subsystem clock and to operate the system with low power consumption (122
µ s @32.768 kHz operation). Also, use of a circuit to multiply the subsystem clock by 4 can be selected via
the subclock select register (SSCK) (15.3 µ s when a circuit to multiply the subsystem clock by 4 is used).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with PCC. The HALT mode
can be used. However, the STOP mode cannot be used (subsystem clock oscillation cannot be stopped).
(f)
The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to
8-bit timer 51, the watch timer, the clock output functions, and the LCD controller/driver only. Thus 8-bit timer
51, the watch function, the clock output function, and the LCD controller/driver can also be continued in the
standby state. However, since all other peripheral hardware operate with the main system clock, the peripheral
hardware also stops if the main system clock is stopped (except when a clock is input externally).
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CHAPTER 5 CLOCK GENERATOR
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User's Manual U15798EJ2V0UD
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