Figure 3-6. Correspondence Between Data Memory and Addressing ( µ PD78F0354, 78F0354Y)
F F F F H
Special function registers (SFRs)
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
General-purpose
registers 32 × 8 bits
F E E 0 H
F E D F H
Internal high-speed RAM
1,024 × 8 bits
F E 2 0 H
F E 1 F H
F B 0 0 H
F A F F H
Reserved
F A 2 8 H
F A 2 7 H
LCD display RAM
40 × 8 bits
F A 0 0 H
F 9 F F H
Reserved
F 8 0 0 H
F 7 F F H
Internal expansion RAM
512 × 8 bits
F 6 0 0 H
F 5 F F H
Reserved
8 0 0 0 H
7 F F F H
Flash memory
32,768 × 8 bits
0 0 0 0 H
Note
The area not used as LCD display data can be used as normal RAM.
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CHAPTER 3 CPU ARCHITECTURE
SFR addressing
Register addressing
Note
User's Manual U15798EJ2V0UD
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Based indexed
addressing