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CHAPTER 17 SERIAL INTERFACE IIC0 ( µ PD780344Y, 780354Y SUBSERIES ONLY)
Figure 17-22. Example of Slave to Master Communication
Processing by master device
IIC0 ← address
IIC0
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
STT0
L
SPT0
WREL0
INTIIC0
TRC0
Transfer lines
1
SCL0
SDA0
A6
Start condition
Processing by slave device
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
ACKE0
L
MSTS0
STT0
L
L
SPT0
WREL0
L
INTIIC0
TRC0
Note To cancel master wait, write FFH to IIC0 or set WREL0.
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(1) Start condition ~ address
2
3
4
5
6
7
A5
A4
A3
A2
A1
A0
User's Manual U15798EJ2V0UD
IIC0 ← FFH Note
Note
8
9
1
2
R
D7
D6
IIC0 ← data
3
4
5
6
D5
D4
D3
D2
357
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