NEC mPD780344 Series User Manual page 20

Figure No.
5-6 External Circuit of Subsystem Clock Oscillator .................................................................................... 119
5-7 Examples of Incorrect Resonator Connection ..................................................................................... 120
5-8 Main System Clock Stop Function ....................................................................................................... 123
5-9 System Clock and CPU Clock Switching ............................................................................................. 126
6-1 Block Diagram of 16-Bit Timer/Event Counter 0 .................................................................................. 128
6-2 Format of 16-Bit Timer Mode Control Register 0 (TMC0) .................................................................... 132
6-3 Format of Capture/Compare Control Register 0 (CRC0) ..................................................................... 133
6-4 Format of 16-Bit Timer Output Control Register 0 (TOC0) .................................................................. 134
6-5 Format of Prescaler Mode Register 0 (PRM0) ..................................................................................... 135
6-6 Format of Port Mode Register 3 (PM3) ................................................................................................ 136
6-7 Control Register Settings for Interval Timer Operation ........................................................................ 137
6-8 Interval Timer Configuration Diagram .................................................................................................. 138
6-9 Timing of Interval Timer Operation ....................................................................................................... 138
6-10 Control Register Settings for PPG Output Operation ........................................................................... 139
6-11 Configuration of PPG Output ............................................................................................................... 140
6-12 PPG Output Operation Timing ............................................................................................................. 140
6-13 Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ................................................................................................................... 141
6-14 Configuration Diagram for Pulse Width Measurement by Free-Running Counter ................................
6-15 Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified) ...................................................................... 142
6-16 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ............
6-17 Capture Operation of CR01 with Rising Edge Specified ...................................................................... 144
6-18 Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ................................................................................................................. 144
6-19 Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers ......................................................................................................................... 145
6-20 Timing of Pulse Width Measurement Operation by Free-Running Counter
and Two Capture Registers (with Rising Edge Specified) .................................................................... 146
6-21 Control Register Settings for Pulse Width Measurement by Means of Restart ................................... 147
6-22 Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) ................................................................................................................ 147
6-23 Control Register Settings in External Event Counter Mode ................................................................. 148
6-24 External Event Counter Configuration Diagram ................................................................................... 149
6-25 External Event Counter Operation Timing (with Rising Edge Specified) .............................................
6-26 Control Register Settings in Square-Wave Output Mode ..................................................................... 150
6-27 Square-Wave Output Operation Timing ............................................................................................... 150
6-28 Start Timing of 16-Bit Timer Counter 0 (TM0) ...................................................................................... 151
6-29 Timing After Change of Compare Register During Timer Count Operation ......................................... 151
6-30 Capture Register Data Retention Timing ............................................................................................. 152
6-31 Operation Timing of OVF0 Flag ........................................................................................................... 153
7-1 Block Diagram of Timer A0 .................................................................................................................. 158
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User's Manual U15798EJ2V0UD
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