NEC mPD780344 Series User Manual page 304

(d) Reception
Receive operations are executed via level detection.
The receive operation is enabled when "1" is set to bit 6 (RXE0) of asynchronous serial interface mode
register 0 (ASIM0), and input via the RxD0 pin is sampled.
The serial clock specified by BRGC0 is used to sample the RxD0 pin.
When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing
signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the
RxD0 pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the
5-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized,
the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame
is completed.
Once reception of one data frame is completed, the receive data in the shift register is transferred to receive
buffer register 0 (RXB0) and INTSR0 (receive completion interrupt request) occurs.
If the RXE0 bit is reset (to "0") during a receive operation, the receive operation is stopped immediately. At
this time, the contents of RXB0 and ASIS0 do not change, nor does INTSR0 or INTSER0 (receive error
interrupt request) occur.
Figure 16-9 shows the timing of the asynchronous serial interface receive completion interrupt request.
Figure 16-9. Timing of Asynchronous Serial Interface Receive Completion Interrupt Request
RxD0 (input)
INTSR0
Caution Be sure to enable receive operations after setting the RxD0 pin input to high level; a receive
operation is immediately started if receive operations are enabled when the RxD0 pin input
is at low level.
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CHAPTER 16 SERIAL INTERFACE UART0
START D0 D1 D2
User's Manual U15798EJ2V0UD
D6 D7 Parity STOP