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(2) LCD clock control register 3 (LCDC3)
This register is used to select the LCD source clock and frame frequency.
It is set by an 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 18-4. Format of LCD Clock Control Register 3 (LCDC3)
Address: FF91H After reset: 00H
Symbol
7
LCDC3
0
LCDC33
0
0
1
1
LCDC31
0
0
1
1
Caution Do not rewrite LCDC3 while the LCD is operating. Be sure to set this bit while LCDON = 0, SCOC
= 0, and VLCON = 0.
Remark Figures in parentheses are for operation with f
Table 18-4 shows the frame frequency if f
the relationship between the reference clock that generates the frame frequency, and the frame frequency.
Frame Frequency
Display duty
Static
1/3 duty
1/4 duty
Note Set so that the frame frequency is 128 Hz or lower.
366
CHAPTER 18 LCD CONTROLLER/DRIVER
R/W
6
5
0
0
LCDC32
0
f
(32.768 kHz)
XT
6
1
f
/2
(156.25 kHz)
X
7
0
f
/2
(78.125 kHz)
X
8
1
f
/2
(39.0625 kHz)
X
LCDC30
Selection of reference clock generating frame frequency
6
0
f
/2
LCD
7
1
f
/2
LCD
8
0
f
/2
LCD
9
1
f
/2
LCD
(32.768 kHz) is used as the source clock (f
XT
Table 18-4. Frame Frequency
Reference Clock Generating
Frame Frequency
User's Manual U15798EJ2V0UD
4
3
2
0
LCDC33
LCDC32
Source clock selection (f
= 10 MHz or f
= 32.768 kHz
X
XT
9
8
f
/2
f
/2
XT
XT
64 Hz
128 Hz
21 Hz
43 Hz
16 Hz
32 Hz
1
0
LCDC31
LCDC30
)
LCD
), and Figure 18-5 shows
LCD
7
f
/2
f
/2
XT
XT
Note
Note
256 Hz
512 Hz
Note
85 Hz
171 Hz
64 Hz
128 Hz
6
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