Table of Contents
Advertisement
Figure 8-4. Format of Timer Clock Select Register 51 (TCL51)
Address: FF74H
After reset: 00H
Symbol
7
TCL51
0
TCL512
0
0
0
0
1
1
1
1
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to set bits 3 to 7 to 0.
Remarks 1. f
: Main system clock oscillation frequency
X
2. Figures in parentheses are for operation with f
(2) 8-bit timer mode control register 5n (TMC5n: n = 0, 1)
TMC5n is a register which sets the following.
<1> 8-bit timer counter 5n (TM5n) count operation control
<2> 8-bit timer counter 5n (TM5n) operation mode selection
<3> Timer output F/F (flip flop) status setting
<4> Active level selection in timer F/F control or PWM (free-running) mode.
<5> Timer output control
TMC5n is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the value of this register to 00H.
Figure 8-5 shows the TMC5n format.
192
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50, 51
R/W
6
5
4
0
0
0
TCL511
TCL510
0
0
TI51 falling edge
0
1
TI51 rising edge
1
0
f
/2 (5 MHz)
X
3
1
1
f
/2
X
5
0
0
f
/2
X
7
0
1
f
/2
X
9
1
0
f
/2
X
1
1
f
(32.768 kHz)
XT
User's Manual U15798EJ2V0UD
3
2
0
TCL512
Count clock selection
(1.25 MHz)
(313 kHz)
(78.1 kHz)
(19.5 kHz)
= 10 MHz, f
= 32.768 kHz
X
XT
1
0
TCL511
TCL510
Advertisement
Table of Contents
