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Data memory STOP mode low power supply voltage data retention characteristics (T
Parameter
Symbol
Data retention power V
DDDR
supply voltage
Data retention
I
DDDR
power supply current
Release signal set
t
SREL
time
Oscillation
t
WAIT
stabilization wait time
12
Note Selection of 2
/f
oscillation stabilization time select register (OSTS).
Data retention timing (STOP mode release by RESET)
V
DD
STOP instruction execution
RESET
Data retention timing (standby release signal: STOP mode release by interrupt request signal)
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
476
CHAPTER 25 ELECTRICAL SPECIFICATIONS
V
= 2.7 V
DDDR
Release by RESET
Release by interrupt request
14
15
16
, 2
/f
, 2
/f
, 2
/f
, and 2
X
X
X
X
STOP mode
Data retention mode
V
DDDR
STOP mode
Data retention mode
V
DDDR
User's Manual U15798EJ2V0UD
Conditions
17
/f
is possible using bits 0 to 2 (OSTS0 to OSTS2) of the
X
Internal reset operation
t
SREL
t
SREL
= −40 to +85°C)
A
MIN.
TYP.
MAX. Unit
1.6
5.5
µ A
0.1
30
0
17
2
/f
X
Note
HALT mode
Operating mode
t
WAIT
HALT mode
Operating mode
t
WAIT
V
µ s
s
s
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