NEC mPD780344 Series User Manual page 391

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction
is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon application of RESET input.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction.
RESET input sets the values of these registers to 00H.
Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
Address: FFE0H After reset: 00H R/W
Symbol 7
IF0L PIF6
Address: FFE1H After reset: 00H R/W
Symbol 7
IF0H WTNIIF0
Address: FFE2H After reset: 00H R/W
Symbol 7
IF1L WTNIF0
XXIFX
0
1
Note µ PD780344Y, 780354Y Subseries only
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as the interval timer.
If watchdog timer mode 1 is used, set the WDTIF flag to 0.
2. When operating a timer, serial interface, or A/D converter after standby release, run it once
after clearing the interrupt request flag, as the interrupt request flag may be set by noise.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and
then the interrupt routine is started.
CHAPTER 19 INTERRUPT FUNCTIONS
6 5
PIF5 PIF4 PIF3
6 5
Note
IICIF0 CSIIF3 CSIIF1
6 5
ADIF0 TMIF51 TMIF50
No interrupt request signal is generated
Interrupt request signal is generated, interrupt request status
User's Manual U15798EJ2V0UD
4 3 2
PIF2 PIF1
4 3 2
STIF0 SRIF0
4 3 2
TMIFB0 TMIFA0
Interrupt request flag
1 0
PIF0 WDTIF
1 0
SERIF0 KRIF
1 0
TMIF01 TMIF00
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