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Table 18-2 shows the maximum number of pixels that can be displayed in each display mode.
Bias Mode
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1/3
18.2 LCD Controller/Driver Configuration
The LCD controller/driver consists of the following hardware.
Item
Display output
Control registers
CHAPTER 18 LCD CONTROLLER/DRIVER
Table 18-2. Maximum Number of Pixels Displayed
Time Division
Common Signals
Static
SCOM0
3
COM0 to COM2
4
COM0 to COM3
Table 18-3. LCD Controller/Driver Configuration
Segment signal: 40 lines Dynamic/static alternated: 12 lines
Common signal: 4 lines (for dynamic display)
1 line (for static display)
LCD display mode register 3 (LCDM3)
LCD clock control register 3 (LCDC3)
LCD gain adjust register 0 (VLCG0)
Static/dynamic display switching register 3 (SDSEL3)
Pin function switching registers (PF8 to PF11)
User's Manual U15798EJ2V0UD
Maximum Number of Pixels
12 (12 segments × 1 common)
120 (40 segments × 3 commons)
160 (40 segments × 4 commons)
Configuration
Segment/output port:
28 lines
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