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(2) µ PD780344, 780354, 780344Y, 780354Y
Set the value of the memory size switching register (IMS) to 48H, and the value of the internal expansion RAM
size switching register (IXS) to 0BH (default setting: IMS = CFH, IXS = 0CH).
Figure 3-2. Memory Map ( µ PD780344, 780354, 780344Y, 780354Y)
F F F F H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F D 0 0 H
F C F F H
F A 2 8 H
F A 2 7 H
Data
F A 0 0 H
memory
F 9 F F H
space
F 8 0 0 H
F 7 F F H
F 6 0 0 H
F 5 F F H
8 0 0 0 H
7 F F F H
Program
memory space
0 0 0 0 H
Note
The area not used for LCD display data can be used as normal RAM.
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CHAPTER 3 CPU ARCHITECTURE
Special function
registers (SFRs)
256 × 8 bits
General-purpose
registers 32 × 8 bits
Internal high-speed RAM
512 × 8 bits
Reserved
LCD display RAM
40 × 8 bits
Note
Reserved
Internal expansion RAM
512 × 8 bits
Reserved
Internal ROM
32,768 × 8 bits
User's Manual U15798EJ2V0UD
7 F F F H
Program area
1 0 0 0 H
0 F F F H
CALLF entry area
0 8 0 0 H
0 7 F F H
Program area
0 0 8 0 H
0 0 7 F H
CALLT table area
0 0 4 0 H
0 0 3 F H
Vector table area
0 0 0 0 H
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