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2
(f) I
C bus mode
Parameter
SCL0 clock frequency
Bus free time
(between stop and start condition)
Note 1
Hold time
SCL0 clock low-level width
SCL0 clock high-level width
Start/restart condition setup time
Data hold time
CBUS compatible master
2
I
C bus
Data setup time
SDA0 and SCL0 signal rise time
SDA0 and SCL0 signal fall time
Stop condition setup time
Capacitive load per each bus line
Spike pulse width controlled by input filter
Notes 1. On the start condition, the first clock pulse is generated after the hold period.
2. To fulfill the undefined area of the SCL0 falling edge, it is necessary for the device to provide internally
an SDA0 signal (on V
3. If the device does not extend the SCL0 signal low hold time (t
needs to be fulfilled.
4. The high-speed mode I
conditions described below must be satisfied.
•
If the device does not extend the SCL0 signal low state hold time
≥ 250 ns
t
SU:DAT
•
If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t
t
= 1,000 + 250 = 1,250 ns by standard mode I
SU:DAT
5. Cb: Total capacitance per bus line (unit: pF)
470
CHAPTER 25 ELECTRICAL SPECIFICATIONS
Symbol
Standard Mode
MIN.
f
0
SCL
t
4.7
BUF
t
4.0
HD:STA
t
4.7
LOW
t
4.0
HIGH
t
4.7
SU:STA
t
5.0
HD:DAT
Note 2
0
t
250
SU:DAT
−
t
R
−
t
F
t
4.0
SU:STO
−
Cb
−
t
SP
of the SCL0 signal) with at least 300 ns of hold time.
IHmin.
2
C bus is available in the standard mode I
User's Manual U15798EJ2V0UD
High-Speed Mode
MAX.
MIN.
100
0
−
1.3
−
0.6
−
1.3
−
0.6
−
0.6
−
−
−
Note 2
0
0.9
−
Note 4
100
Note 5
1,000
20 + 0.1Cb
Note 5
300
20 + 0.1Cb
−
0.6
−
400
−
0
), only maximum data hold time t
LOW
2
C bus system. At this time, the
2
C bus specification).
Unit
MAX.
400
kHz
−
µ s
µ s
−
−
µ s
−
µ s
−
µ s
−
µ s
Note 3
µ s
−
ns
300
ns
300
ns
−
µ s
400
pF
50
ns
HD:DAT
+
Rmax.
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