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CHAPTER 13 10-BIT A/D CONVERTER ( µ PD780354, 780354Y SUBSERIES)
13.2 10-Bit A/D Converter Configuration
10-bit A/D converter consists of the following hardware.
Item
Analog input
Registers
Control registers
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is hold (end of A/D conversion), the SAR contents are transferred to
A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
This is a 16-bit register which stores the A/D conversion results. Lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register.
The result is stored in ADCR0 in order from the most significant bit (MSB). The higher 8 bits of the conversion
result are input to FF0FH and the lower 2 bits of the conversion result are input to FF0EH.
ADCR0 is read by a 16-bit memory manipulation instruction.
RESET input sets the value of this register to 0000H.
FF0FH
Symbol
ADCR0
Caution When writing is performed to A/D converter mode register 0 (ADM0) and analog input channel
specification register 0 (ADS0), the contents of ADCR0 may become undefined. Read the
conversion result following conversion completion before writing to ADM0, ADS0. Using a
timing other than the above may cause an incorrect conversion result to be read.
(3) Sample & hold circuit
The sample & hold circuit samples the signal input to the analog input pin selected by the selector when A/D
conversion is started. This circuit holds the sampled analog input voltage value during A/D conversion.
(4) Voltage comparator
The voltage comparator compares the sampled analog input voltage to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected between AV
analog input.
Table 13-1. 10-Bit A/D Converter Configuration
8 channels (ANI0 to ANI7)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
and AV
DD
User's Manual U15798EJ2V0UD
Configuration
FF0EH
0
0
0
0
0
0
, and generates a voltage to be compared to the
SS
Address
After reset
R/W
FF0EH,
0000H
R
FF0FH
245
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