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Table No.
12-1
8-Bit A/D Converter Configuration ....................................................................................................... 224
12-2
Settings of ADCS0 and ADCE0 ........................................................................................................... 228
12-3
Resistances and Capacitances of Equivalent Circuit (Reference Values) ........................................... 243
13-1
10-Bit A/D Converter Configuration ..................................................................................................... 245
13-2
Settings of ADCS0 and ADCE0 ........................................................................................................... 248
13-3
Resistances and Capacitances of Equivalent Circuit (Reference Values) ........................................... 264
14-1
Configuration of Serial Interface SIO3 ................................................................................................. 266
15-1
Configuration of Serial Interface CSI1 ................................................................................................. 273
16-1
Configuration of Serial Interface (UART0) ........................................................................................... 288
16-2
Relationship Between 5-Bit Counter's Source Clock and "n" Value ..................................................... 298
16-3
Relationship Between Main System Clock and Baud Rate ................................................................. 299
16-4
Causes of Receive Errors .................................................................................................................... 305
17-1
Configuration of Serial Interface IIC0 ................................................................................................... 309
17-2
INTIIC0 Timing and Wait Control ......................................................................................................... 344
17-3
Extension Code Bit Definitions ............................................................................................................ 345
17-4
Status During Arbitration and Interrupt Request Generation Timing ................................................... 347
17-5
Wait Periods ......................................................................................................................................... 348
18-1
Segment Signals and Common Signals .............................................................................................. 360
18-2
Maximum Number of Pixels Displayed ................................................................................................ 361
18-3
LCD Controller/Driver Configuration .................................................................................................... 361
18-4
Frame Frequency ................................................................................................................................. 366
18-5
COM Signals ........................................................................................................................................ 372
18-6
Output Voltages of V
18-7
Selection and Non-Selection Voltages (SCOM0) ................................................................................. 376
18-8
Selection and Non-Selection Voltages (COM0 to COM2) .................................................................... 379
18-9
Selection and Non-Selection Voltages (COM0 to COM3) .................................................................... 382
19-1
Interrupt Source List ............................................................................................................................ 387
19-2
Flags Corresponding to Interrupt Request Sources ............................................................................ 390
19-3
Time from Generation of Maskable Interrupt Until Servicing ............................................................... 399
19-4
Interrupt Request Enabled for Nesting During Interrupt Servicing ....................................................... 402
20-1
HALT Mode Operating Statuses .......................................................................................................... 408
20-2
Operation After HALT Mode Release ................................................................................................... 410
20-3
HALT Mode Release Condition and Necessity of NOP Instruction Setting
When Subclock Multiplied by 4 Is Used ( µ PD78F0354, 78F0354Y Only) ........................................... 411
20-4
STOP Mode Operating Statuses ......................................................................................................... 412
20-5
Operation After STOP Mode Release .................................................................................................. 414
28
LIST OF TABLES (2/3)
Title
to V
Pins .................................................................................................... 375
LC0
LC2
User's Manual U15798EJ2V0UD
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