Maskable Interrupt Request Acknowledge Operation - NEC mPD780344 Series User Manual

8-bit single-chip microcontrollers
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19.4.2 Maskable interrupt request acknowledge operation

A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask
(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if in
the interrupt enable state (when IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). Even if the EI instruction is
executed while a non-maskable interrupt servicing program is being executed (NMIS = 1), non-maskable and
maskable interrupt requests are not acknowledged. The time from generation of a maskable interrupt request until
interrupt servicing is performed is shown in Table 19-3 below.
For the interrupt request acknowledge timing, see Figures 19-11 and 19-12.
Table 19-3. Time from Generation of Maskable Interrupt Until Servicing
When ××PR = 0
When ××PR = 1
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
CPU
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more maskable interrupt requests have the
same priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 19-10 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded
into the PC and branched.
Return from an interrupt is possible with the RETI instruction.
CHAPTER 19 INTERRUPT FUNCTIONS
Minimum Time
7 clocks
8 clocks
(f
: CPU clock)
CPU
User's Manual U15798EJ2V0UD
Note
Maximum Time
32 clocks
33 clocks
399

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