Spia Ch.n Control Register - Epson S1C17W03 Technical Manual

13 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Bits 7–6 Reserved
Bit 5 PUEN
This bit enables pull-up/down of the input pins.
1 (R/W): Enable pull-up/down
0 (R/W): Disable pull-up/down
For more information, refer to "Input Pin Pull-Up/Pull-Down Function."
Bit 4 NOCLKDIV
This bit selects SPICLKn in master mode. This setting is ineffective in slave mode.
1 (R/W): SPICLKn frequency = CLK_SPIAn frequency ( = 16-bit timer operating clock frequency)
0 (R/W): SPICLKn frequency = 16-bit timer output frequency / 2
For more information, refer to "SPIA Operating Clock."
Bit 3 LSBFST
This bit configures the data format (input/output permutation).
1 (R/W): LSB first
0 (R/W): MSB first
Bit 2 CPHA
Bit 1 CPOL
These bits set the SPI clock phase and polarity. For more information, refer to "SPI Clock (SPICLKn)
Phase and Polarity."
Bit 0 MST
This bit sets the SPIA operating mode (master mode or slave mode).
1 (R/W): Master mode
0 (R/W): Slave mode
Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0.

SPIA Ch.n Control Register

Register name Bit
SPInCTL 15–8 –
7–2 –
1
0
Bits 15–2 Reserved
13-12
Table 13.7.1 Data Bit Length Settings
SPInMOD.CHLN[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
0x00
SFTRST 0
MODEN 0
Seiko Epson Corporation
Data bit length
16 bits
15 bits
14 bits
13 bits
12 bits
11 bits
10 bits
9 bits
8 bits
7 bits
6 bits
5 bits
4 bits
3 bits
2 bits
Setting prohibited
Reset R/W
– R –
– R
H0 R/W
H0 R/W
S1C17W03/W04 TECHNICAL MANUAL
Remarks
(Rev. 1.2)