ARM ETB11 Technical Reference Manual page 7

List of Figures
ETB11 Technical Reference Manual
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 4-1
Figure 4-2
Figure 4-3
ARM DDI 0275D
Key to timing diagram conventions ............................................................................. xii
System-on-Chip debug implementation .................................................................... 1-2
ETB11 module block diagram ................................................................................... 2-3
Trace capture operation ............................................................................................ 2-6
Trace read operation ................................................................................................. 2-7
BIST interface block diagram .................................................................................. 2-11
Read access from Trace RAM timing diagram ........................................................ 2-16
Write access to Trace RAM timing diagram ............................................................ 2-16
Example synchronizer ............................................................................................. 2-17
Synchronization logic between HCLK and CLK domains ....................................... 2-20
Software read cycle with asynchronous CLK and HCLK ........................................ 2-21
Software read cycle with synchronous CLK and HCLK .......................................... 2-22
Software write cycle with asynchronous CLK and HCLK ........................................ 2-24
Software write cycle with synchronous CLK and HCLK .......................................... 2-25
AHB interface signals ................................................................................................ 4-2
CLK domain signals .................................................................................................. 4-4
IEEE1149.1 interface signals .................................................................................... 4-6
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