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Index
Integrating
generic trace port interface B-3
signals B-2
Interfaces, primary 2-2
J
JTAG 1-4
N
Numerical conventions xiii
P
Primary interfaces 2-2
Product revision status x
Public instructions 2-13
R
RAM Data Register 3-7
RAM Depth Register 3-5
RAM overflow
FULL A-3
RAM Read Pointer Register 3-7
RAM Width Register 3-5
RAM Write Pointer Register 3-8
Read address generation 2-10
Read transfer
asynchronous 2-19
synchronous 2-22
Register fields 3-2
Register map 3-2
Registers 3-4
Control 3-10
Identification 3-4
Instruction 2-13
RAM Data 3-7
RAM Depth 3-5
RAM Read Pointer 3-7
RAM Width 3-5
RAM Write Pointer 3-8
Status 3-6
Resets 2-17
Index-2
Revision status x
S
Signal descriptions A-2, A-3
Signal naming conventions xii
Signal properties and requirements A-2
Signals
ACQCOMP A-3, B-2
CLK A-3
DBGTCK A-3
DBGTCKEN A-3
DBGTDI A-3
DBGTMS A-3
FULL A-3, B-2
HADDR A-3
HCLK A-3, B-2
HCLKEN A-3, B-2
HRDATAMEM A-3
HREADY A-3
HREADYMEM A-3
HRESETn A-3
HRESPMEM A-4
HSELMEM A-4, B-2
HSELREG A-4, B-2
HSIZE A-4
HTRANS A-4
HWDATA A-4, B-4
HWRITE A-4
MBISTADDR A-4
MBISTCE A-4
MBISTDIN A-4
MBISTDOUT A-4
MBISTWE A-5
MTESTON A-5
nDBGTDOEN A-5
nDBGTRST A-5
nRESET A-5
PORTSIZE A-5, B-3
PROTOCOL A-5, B-3
SBYPASS A-5, B-2
SCANMODE A-5
SE A-5
SWEN A-5
TRACEOUTPUT A-5, B-3
TRACEVALID A-5, B-3
TRIGGER A-5, B-3
Software access to ETB11 3-11
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Software read cycle
asynchronous 2-21
synchronous 2-22
Software write cycle
asynchronous 2-24
synchronous 2-25
Status Register 3-6
Supported public instructions 2-13
T
TAP controller 2-12
Test data registers
bypass 2-12
scan chain 0 2-13
Timing diagram conventions xii
Trace capture operation 2-6
Trace RAM interface 2-15
read access 2-15
write access 2-16
Trace read operation 2-7
TRACEOUTPUT
bus B-3
pin connections B-3
Trigger delay counter 2-9
Typographical conventions xi
W
Write address generation 2-10
Write transfer
asynchronous 2-22
synchronous 2-24
ARM DDI 0275D
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