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Timing Requirements
4.3
IEEE1149.1 interface
4-6
The IEEE1149.1 interface signals are shown in Figure 4-3.
The timing requirements for the IEEE1149.1 interface trace data signals are listed in
Table 4-3. All figures are expressed as percentages of the DBGTCK period at
maximum operating frequency.
Note
A 0% figure in Table 4-3 indicates the hold time to clock edge plus the maximum clock
skew for internal clock buffering.
Parameter
Description
T
Rising DBGTCK to DBGTDO output valid
ovttrans
T
DBGTDO output hold time from DBGTCK rising
ohttrans
T
JTAG inputs setup to rising DBGTCK
isttrans
T
JTAG inputs hold from rising DBGTCK
ihttrans
T
nDBGTRST input setup to rising DBGTCK
isntrst
T
nDBGTRST input hold from rising DBGTCK
ihntrst
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Figure 4-3 IEEE1149.1 interface signals
Table 4-3 IEEE1149.1 interface timing requirements
Max
Min
40%
-
-
>0%
-
40%
-
0%
-
40%
-
0%
ARM DDI 0275D
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